Field of the Invention
Embodiments of the present invention relate to a semiconductor device with power semiconductor elements, controlling a load current flowing in a mutual-inductive load such as a stepping motor, and an integrated circuit, detecting an abnormality in the load for protecting the power semiconductor elements, being integrated in the same semiconductor substrate.
Background
FIG. 7A is a diagram showing the whole configuration of the principal part of a stepping motor. FIG. 7B is a diagram showing the arrangement of a rotor 97 and coils 90 of the stepping motor. The stepping motor is provided with the rotor 97 and the four coils 90 (91 to 94) for rotating the rotor 97. As is shown in FIG. 7A, control circuits 501a to 501d are provided with their respective output stage nMOSFETs 51a to 51d. The output stage nMOSFETs 51a to 51d carry out control of currents flowing in the coils 91 to 94 connected thereto, respectively. In addition, the output stage nMOSFETs 51a to 51d have their respective parasitic diodes (shown without reference numerals) connected in parallel thereto. Furthermore, the control circuits 501a to 501d are provided with their respective various kinds of detection circuits (an overheating detection circuit and an overcurrent detection circuit etc.) and protection circuits (not shown). In addition, a battery B as a power supply becomes necessary.
As is shown in FIG. 7B, the four coils 91 to 94 are arranged around the rotor 97. The two opposed coils 91 and 93 are wound around one core 95 of iron, for example, to be iron-core coils having mutual inductance. Similarly, the two opposed coils 92 and 94 are wound around one core 96 of iron to be iron-core coils having mutual inductance. Thus, each of the iron-core coils 91 and 93 is referred to as a mutual-inductive load, and each of the iron-core coils 92 and 94 is also referred to as a mutual-inductive load. The output stage nMOSFETs 51a and 51c, connected to the two (a pair of the) coils 91 and 93, respectively, wound onto the one core 95, mutually carry out complementary operations (operations carried out between two so that when one is turned-on, the other is turned-off). Moreover, the output stage nMOSFETs 51b and 51d, connected to the two (a pair of the) coils 92 and 94, respectively, wound onto the one core 96, also mutually carry out complementary operations. The four coils 91 to 94 are arranged around the rotor 97 to give a rotating force to the rotor 97.
The one coil 90 and the one output stage nMOSFET 51 of the one control circuit 501 form one arm. Here, the reference numeral 90 is that used when the coils 91 to 93 are generally named, the reference numeral 50 is that used when the output stage nMOSFETs 51a to 51d are generally named, and the reference numeral 501 is that used when the control circuits 501a to 501d are generally named.
The stepping motor is controlled by four arms of first arm to fourth arm. In each of the first arm to the fourth arm, through its own one of the coils 91 to 94 as the mutual-inductive loads, a load current flows. Each arm is provided with one control circuit 501. The stepping motor provided with the arms is used for, for example, exhaust gas recirculation of a vehicle etc. Hence, in the following, each of the arms is referred to as an EGR. The term EGR is an abbreviation of Exhaust Gas Recirculation. Here, the first arm to the fourth arm are referred to as EGR1 to EGR4, respectively, and are formed with the coil 91 to the coil 94 and the output stage nMOSFET 51a to the output stage nMOSFET 51d, respectively.
The control circuit 501 has four terminals of an IN terminal (IN) as an input terminal, an OUT terminal (OUT) as an output terminal, an ST terminal (ST) as a status terminal (state output terminal), and a GND terminal (GND) as a grounding terminal.
FIG. 8 is a block diagram showing the first arm EGR1 and the third arm EGR3 shown in FIG. 7A with the configurations thereof being made simplified. When the first arm EGR1 is turned-off and the third arm EGR3 is turned-on, in a transient state immediately thereafter, a current flows in a path shown by arrows in dotted lines in the direction of charging the battery B through the parasitic diode (shown without reference numeral) connected in parallel to the output stage nMOSFET 51c shown in FIG. 7A due to the induced electromotive force generated in the iron-core coil 93 as the mutual-inductive load. At this time, the polarity of an OUT3 terminal becomes negative. Thereafter, when the state becomes a steady state, a steady current flows in the iron-core coil 93 (inductive load) through the output stage nMOSFET 51c in the third arm EGR3 already in the turned-on state. Here, the control circuits 501a and 501c of semiconductor devices 500a and 500c explained later, respectively, are driven by signals from a timing generator.
FIG. 9 is a detailed circuit diagram of the control circuit 501 (501a to 501d) shown in FIG. 7A. The circuit configurations of all of the control circuits 501a to 501d are identical. The control circuit 501 is provided with voltage dividing resistors 64 and 65 dividing the voltage at the OUT terminal and the output stage nMOSFET 51 formed of an nMOSFET section 52 and a parasitic diode section 53. In addition, the control circuit 501 is provided with a dynamic clamp Zener diode 54 connected between the drain 52b and the gate 52a of the output stage nMOSFET 51. The dynamic clamp Zener diode 54 is formed of Zener diodes 54a and 54b in inverse-series connection to each other.
The control circuit 501 is provided with an nMOSFET 55a that is connected to the gate 52a of the output stage nMOSFET 51 to form a gate charge extracting circuit at protecting operation 55 that will be explained later. Further, the control circuit 501 is provided with a resistor 63 connected to the drain (shown without reference numeral) of the nMOSFET 55a and a gate charge extracting circuit at normal operation 56 connected to the resistor 63 and is formed of a constant current source 56a (depletion MOSFET 56b). In addition, the control circuit 501 is provided with a logic circuit 57 connected to a connection point 63a of the constant current source 56a and the resistor 63 and connected to each of an overheat detection circuit 59 and an overcurrent detection circuit 60.
To the ST terminal, a Zener diode 66b and an nMOSFET 58a, which is provided for detecting a state whether the load is normally connected or abnormally disconnected due to a break in a wire etc. (broken wire detection), are connected. To the ST terminal, an ST-MOS circuit 58 is further connected which is formed of an nMOSFET 58b transmitting an abnormal signal to the ST terminal when the abnormal signal is outputted from the logic circuit 57.
Moreover, the IN terminal is connected to the cathode of a Zener diode 66c and the logic circuit 57, the GND terminal is connected to the source of each of the nMOSFETs, and the OUT terminal is connected to the drain of the output stage nMOSFET 51 and the voltage dividing resistors 64 and 65.
The ST-MOS circuit 58 detects a break in a wire as follows. When no abnormality occurs in the load (coil 90), the turning-off of the output stage nMOSFET 51 increases the voltage at the OUT terminal connected to the battery B through the load. This increases the voltage taken out from the connection point of the two resistors in the voltage dividing resistors 65 to turn-on the nMOSFET 58a. Since the drain electrode of the nMOSFET 58a is connected to the ST terminal, a state detection signal when no abnormality occurs (under a normal condition) is outputted to the ST terminal.
While, when a break such as burnout of the load (coil 90) connected to the OUT terminal or disengagement of a connector occurs, the load is disconnected from the OUT terminal, by which the voltage of the battery B is held at the section of the load. This causes no increase in the voltage at the OUT terminal and also causes no increase in the voltage taken out from the connection point of the two resistors of the voltage dividing resistors 65 and given to the gate of the nMOSFET 58a through the lead of a broken wire detection line 69. At this time, the nMOSFET 58a is kept in a turned-off state, by which a state detection signal representing a broken state in which the load is disconnected can be outputted from the ST terminal.
In the same ST-MOS circuit 58, the operation of the nMOSFET 58b connected in parallel to the nMOSFET 58a is as follows. When the logic circuit 57 detects an abnormal state such as the overheating or the overcurrent of the nMOSFET 51, the logic circuit 57 outputs an abnormal signal (high logic level, H) to the gate electrode of the nMOSFET 58b. This makes the nMOSFET 58b turned-on, by which a state detection signal (abnormal signal) is outputted to the ST terminal.
To the ST terminal, an unillustrated control device (microcomputer etc.) is externally connected. The control device makes a decision as to whether the load connected to the OUT terminal is in a state without abnormality or in any one of abnormal states described in the foregoing by combining the logical value of the gate signal to the output stage nMOSFET 51, which signal is outputted from the timing generator shown in FIG. 8, and the logical value of the signal outputted from the ST terminal.
FIG. 10 is a cross sectional view showing the principal part of a related semiconductor device 500 (500a to 500b) with the control circuit 501 (501a to 501d) shown in FIG. 6 formed on an n-type semiconductor substrate 70. All of the circuit configurations of the control circuits 501a to 501d in their respective semiconductor devices 500a to 500d are identical. The battery B forming the control circuit 501 is externally provided.
The semiconductor device 500 is provided with the vertical output stage nMOSFET 51. In the semiconductor device 500, a plurality of p-type well regions 71, 73 and 76 are also formed in the surface layer of the n-type semiconductor substrate 70. The semiconductor device 500 is provided with the logic circuit 57, the overheat detection circuit 59 (not shown), and the overcurrent detection circuit 60 (not shown), which are formed in the surface layer of the p-type well region 76 as one of a plurality of the foregoing p-type well regions. In the surface layer of the p-type well region 76, the lateral nMOSFET 55a in the gate charge extracting circuit at protecting operation 55 and the gate charge extracting circuit at normal operation 56 are further provided.
As an n+-type region connected to the GND wiring, an n-type source region 72 (source 52c) of the output stage nMOSFET 51 is provided in the surface layer of the p-type well region 71 as another one of the p-type well regions. Further, an n-type cathode region 74 of the Zener diode 54a (formed in the n-type semiconductor substrate 70) forming the dynamic clamp Zener diode 54 is provided in the surface layer of the p-type well region 73 as the remaining one of the p-type well regions. In addition, an n+-type region 75 is provided which is formed in the surface layer of the n-type semiconductor substrate 70 and is connected to the ground GND.
The ST terminal (ST) is connected to an n-type drain region 79 of the lateral nMOSFET 58b, formed in the p-type well region 76 to form the ST-MOS circuit 58, through a resistor 67e. The IN terminal (IN) is connected to the gate 52a of the output stage nMOSFET 51 through the resistors 67b, 63, and 67a by gate wiring 68. The OUT terminal (OUT) is connected to an electrode formed on the whole bottom surface of the n-type semiconductor substrate 70. The electrode formed on the whole bottom surface of the n-type semiconductor substrate 70 becomes the drain electrode of the output stage nMOSFET 51.
The GND terminal (GND) is connected to the n-type source region (shown without reference numeral) of the lateral nMOSFET 55a forming the gate charge extracting circuit at protecting operation 55. The GND terminal is also connected to an n-type source region 78 of the depletion MOSFET 56b to be the constant current source 56a forming the gate charge extracting circuit at normal operation 56. The GND terminal is further connected to the n-type source region (shown without reference numeral) of a lateral nMOSFETs 57a in the logic circuit 57, to the n-type source region (shown without reference numeral) of the nMOSFET 58b (58a) having the n-type drain region 79 connected to the ST terminal (ST), and to the p-type well region 76.
In addition, the n-type drain region (shown without reference numeral) of the lateral nMOSFET 55a and the n-type drain region 77 of the depletion MOSFET 56b are connected to the gate wiring 68. Moreover, a Zener diode 81 for surge protection connected between the IN terminal and the GND terminal and a Zener diode 82 connected between the GND terminal and the ST terminal are provided.
Both of the p-type well region 71 and the n-type source region 72 (source 52c) of the output stage nMOSFET 51 are also connected to the GND terminal. With the p-type well region 71 and the n-type semiconductor substrate 70, the parasitic diode section 53 of the output stage nMOSFET 51 is formed.
The overheat detection circuit 59, the overcurrent detection circuit 60, the logic circuit 57, the gate charge extracting circuit at protecting operation 55, and the gate charge extracting circuit at normal operation 56, all of which are shown in FIG. 9, are formed in the p-type well region 76 shown in FIG. 10 with each being kept at specified distances away from one another to be self-isolated.
FIG. 11 is a waveform diagram showing the waveforms of input voltages VIN1 to VIN 4 to the first arm EGR1 to the fourth arm EGR4, respectively, shown in FIG. 7A.
The phases of the input voltage VIN1 to the first arm EGR1, the input voltage VIN2 to the second arm EGR2, the input voltage VIN3 to the third arm EGR3, and the input voltage VIN4 to the fourth arm EGR4, respectively, have delays by a time one-half of the pulse width of the input voltage VIN for each thereof. The input voltage VIN is transmitted to the gate wiring 68 to become the gate voltage of the output stage nMOSFET 51. When the input voltage VIN is at an H level, a load current flows in the output stage nMOSFET 51 of the arm EGR to bring the arm EGR into a turned-on state. With the first arm EGR1 to the fourth arm EGR4 brought into turned-on states in order, the rotor 97 is rotated, by which the stepping motor formed of the coils 90 and the rotor 97 carries out a rotary operation. By the rotary operation of the stepping motor, the opening and closing of a valve (not shown) is carried out which is provided in a flow path through which an exhaust gas of a vehicle flows, for example, by which the recirculation of the exhaust gas is carried out.
The output stage nMOSFET 51a forming the first arm EGR1 and the output stage nMOSFET 53a forming the third arm EGR3 carry out complementary operations in which when one is in a turned-on state, the other one is in a turned-off state. That is, the operations of the first arm EGR1 and the third arm EGR3 are complementary to each other. Thus, the time at the falling of the input voltage VIN1 of the first arm EGR1 becomes the time at the rising of the input voltage VIN3 of the third arm EGR3 (at the time of C). The second arm EGR2 and the fourth arm EGR4 also carry out similar complementary operations.
FIG. 12 is a waveform diagram showing the waveforms of the input voltage VIN3, a voltage VST3, a voltage VOUT3, and a current IOUT3 in the control circuit 501c of the third arm EGR3, and the waveforms of the input voltage VIN1, a voltage VST1, a voltage VOUT1, and a current IOUT1 in the control circuit 501a of the first arm EGR1. Here, the input voltage represented by the sign VIN is an input voltage (also referred to as a gate voltage or a control voltage) to the IN terminal as an input terminal represented by the sign IN, the voltage represented by the sign VST is a voltage at the ST terminal as a status terminal represented by the sign ST, the voltage represented by the sign VOUT is a voltage at an OUT terminal as an output terminal represented by the sign OUT and the drain voltage of an output stage nMOSFET 51, and the current represented by the sign IOUT is a current flowing at the OUT terminal, that is, a drain current flowing in the output stage nMOSFET 51. The current IOUT is also a load current flowing in the coil 90 (mutual-inductive load) in the arm EGR.
As is shown in FIG. 12, suppose that a turning-on signal is inputted as the input voltage VIN3, and a turning-off signal is inputted as the input voltage VIN1 at the time t0. Then, the output stage nMOSFET 51a in the first arm EGR1 is made turned-off to bring the current IOUT1 to become zero at the time t1 after a time delay due to the presence of a Miller capacitance and to bring the voltage VOUT1 to be the voltage of the battery B as a power supply voltage. At the time t1 at which the state of the output stage nMOSFET 51a in the first arm EGR1 is changed from the turned-on state to the turned-off state, the state of the output stage nMOSFET 51c in the third arm EGR3 is shifted from the turned-off state to the turned-on state. This makes the voltage VOUT3 fall. In the process after the time t1, due to the influence of the mutual inductance between the coil 93 in the third arm EGR3 and the coil 91 in the first arm EGR1, a current (reverse current) flows in the coil 93 in the third arm EGR3 in the opposite direction from the ground GND toward the battery B. The reverse current lasts for a period determined by the value of the mutual inductance and thereafter, at the time t2 at which the forward current exceeds the reverse current, the current flowing in the third arm EGR3 is switched to a current flowing from the battery B to the ground GND (forward current). The reverse current charges the battery B as a regenerative current.
For preventing the influence of the reverse current explained in the foregoing, a free wheeling diode is sometimes provided for a mutual-inductive load. Moreover, a semiconductor device disclosed in JP-A-2010-110093 is provided with a power semiconductor element for carrying out switching control of a load device and a semiconductor integrated circuit detecting an abnormality of the load device. The semiconductor device further contains a voltage dividing circuit for pulling down, which divides the voltage at the output terminal of a power semiconductor element by resistors for pulling down arranged in series, a MOSFET fed with a power supply voltage from the voltage dividing circuit to detect the disconnection of the load device and a MOSFET carrying out a turning-on or turning-off operation according to an abnormal signal outputted from the semiconductor integrated circuit. In addition, the semiconductor device is provided with a status output terminal outputting the result of the detection of the disconnected state of the load device to the outside. With the configuration, a semiconductor device can be provided to detect a disconnected state of a load in a load driving system. For the load device in this case, a self-inductive load such as a solenoid or a coil is intended to be used.
In JP-A-2000-12853, a semiconductor device is described which has a first switching means turning-on and turning-off a current being made to flow in a load, a current detecting means detecting the current flowing in the load, a second switching means carrying out turning-off and turning-on for opening and closing, respectively, the connection between the current detecting means and the load, and a controlling means controlling the second switching means and the first switching means. In the semiconductor device, the controlling means turns-on the first switching means before turning-on the second switching means at start-up of driving the load and the current detecting means turns-off only the first switching means when an overcurrent is detected. Furthermore, it is described that the configuration can provide a semiconductor device that makes the semiconductor element reliably and quickly turned-off at the short circuit of the load to protect the semiconductor element from the short circuit of the load. Also in this case, a self-inductive load such as a solenoid or a coil is intended to be used.
In JP-A-2011-239242, it is described that when the potential of the ground GND becomes higher than the potential of the output of the semiconductor device due to the reverse current from an inductive load, a voltage is supplied from the drain of a depletion MOSFET always made turned-on to the back gate of a MOSFET so that no parasitic transistor of the MOSFET is made turned-on. In this case, a mutual-inductive load such as a stepping motor is intended to be used.
FIG. 13A is a cross sectional view of the semiconductor device 500c in the third arm EGR3 showing paths P1 and P2 of reverse currents flowing in the semiconductor device 500c with the nMOSFET 51c being turned-on in the turned-off period of the output stage nMOSFET 51a in the first arm EGR1. In the period between the time t1 and the time t2 shown in FIG. 12, reverse currents due to an induced electromotive force (counter electromotive force) generated by the presence of the mutual inductance between the coil 93 in the third arm EGR3 and the coil 91 in the first arm EGR1 flow in the semiconductor device 500c. A path P1 passing through the parasitic diode section 53 of the output stage nMOSFET 51c and a path P2 passing through the n-type semiconductor substrate 70 from the p-type well region 76 become the paths of the reverse currents flowing in the semiconductor device 500c in the third arm EGR3.
While, on the surface of the p-type well region 76, a plurality of n+-type regions are formed, a part of which are connected to an IN3 terminal through the gate wiring 68 or to an ST3 terminal through the resistor 67e. A part of the n+-type regions (n-type collector regions) form a parasitic transistor 88 together with the p-type well region 76 (p-type base region) and the n-type semiconductor substrate 70 (n-type emitter region). FIG. 13B is a schematic cross sectional view showing the operation of the parasitic transistors 88. By the induced electromotive force (counter electromotive force) generated in the coil 93, a forward bias voltage is applied to the p-n junction between the p-type well region 76 connected to the GND terminal at approximately 0V and the n-type semiconductor substrate 70 connected to the OUT3 terminal, by which a reverse current flows from the GND3 terminal to the OUT3 terminal. In this case, a voltage drop V1 is produced at the OUT3 terminal to the GND terminal by, for example, −0.6V which is a built-in potential difference (Vbi) at the p-n junction between the p-type well region 76 and the n-type semiconductor substrate 70. This makes holes injected from the p-type well region 76 to the n-type semiconductor substrate 70 as is shown in FIG. 13B.
Moreover, at the forward-biased p-n junction, electrons are injected from the n-type semiconductor substrate 70 to the p-type well region 76. To the IN3 terminal, a positive voltage of some kind is applied with respect to the GND3 terminal. Hence, a reverse bias voltage is applied to the p-n junction between the n+-type region connected to the IN3 terminal and the p-type well region 76. This allows a part of electrons injected into the p-type well region 76 (p-type base region) to reach the n+-type region connected to the IN3 terminal though the density of the injected electrons is being reduced. With the electrons reaching the n+-type region in this way, the collector current Inpn of the parasitic transistor 88 is to flow from the IN3 terminal to the OUT3 terminal.
Although the ST3 terminal has no voltage applied thereto unlike the IN3 terminal, electrons reach to an n+-type region connected to the ST3 terminal in the same way as that of the electrons to the IN3 terminal. This allows the collector current Inpn to flow from the ST3 terminal to the OUT3 terminal. By the collector current Inpn from the ST3 terminal, the voltage at the ST3 terminal becomes equal to the voltage of the n-type semiconductor substrate 70. Thus, in the period in which the reverse current flows, the level of the voltage at the ST3 terminal becomes an L level equal to the level of the n-type semiconductor substrate 70. In this way, the voltage at the ST3 terminal, coming to be at the L level in the period during which the voltage is originally to be at a high level, causes a microcomputer (MC), to which the voltage at the ST3 terminal is inputted, to perform an erroneous detection.
Moreover, the provision of the free wheeling diodes, as described in the foregoing, causes the number of components to increase to result in a high cost. Furthermore, in each of the semiconductor devices disclosed in JP-A-2010-110093 and JP-A-2000-12853, respectively, a self-inductive load is intended to be used. Therefore, no description is given with respect to the erroneous operation of a parasitic transistor caused when the polarity of the OUT terminal becomes negative in the previously described power semiconductor device connected to the mutual-inductive load.
In addition, in the semiconductor device disclosed in JP-A-2011-239242, the operation of the parasitic transistor in the depletion MOSFET is liable to become unstable when the distribution in the impurity concentration varies in the p-type well region, for example. Thus, when the parasitic transistor in the depletion MOSFET performs no operation, a parasitic transistor in a MOSFET, to which a self-diagnostic output is inputted, is erroneously operated to make it impossible to always maintain the voltage at the DIAG terminal (equivalent to the ST terminal) at a normal voltage.